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Austrochip 2017 Conference Program:
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08:00 - 09:00
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Registration and Breakfast
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09:00 - 09:15
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Conference Opening
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| 09:15 - 09:35 |
Keynote Address
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| 09:40 - 10:00 |
Keynote Address
- Dr. Manfred Sust (RUAG Space)
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| 10:00 - 10:45 |
Session I: Device Modelling and Verification
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Analysis of semiconductor process variations by means of Hierarchical Median Polish
Benjamin Willsch, Julia Hauser, Stefan Dreiner, Andreas Goehlich, Holger Kappert and Holger Vogt
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DC/AC Compact Modeling of TFETs for Circuit Simulation of Logic Cells Based on an Analytical Physics-Based Framework
Fabian Horst, Atieh Farkokhnejad, Michael Graef, Fabian Hosenfeld, Gia Vinh Luong, Chang Liu, Qing-Tai Zhao, Francois Lime, Benjamin Iniguez and Alexander Kloes
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10:45 - 11:05
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Coffee Break, Exhibition
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| 11:05 - 13:00 |
Session II: RF Integrated Circuit Design
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A Compact, Low Power and High Sensitivity E-Band Frequency Divider SiGe HBT MMIC
Aleksey Dyskin, Parisa Harati and Ingmar Kallfass
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CMOS Open-Loop Local Quadrature Phase Generator for 5G Applications
Michael Kalcher and Daniel Gruber
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Receiver Chip in 0.6µm BiCMOS with AGC and LVDS Output Driver
Bernhard Goll, Robert Swoboda and Horst Zimmermann
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A Circuit Technique for Blocker-Induced Modulated Spur Cancellation in 4G LTE Carrier Aggregation Transceivers
Silvester Sadjina, Dufrene Krzysztof, Ram Kanumalli, Mario Huemer and Harald Pretl
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A Review of Ultra-Low-Power and Low-Cost Transceiver Design
Tim Schumacher, Markus Stadelmayer, Thomas Faseth and Harald Pretl
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13:00 - 14:30
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Lunch, Exhibition
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| 14:30 - 14:50 |
Keynote Address
- Dr. Christoph Guger (g.tec)
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| 14:50 - 15:35 |
Session III: Digital Circuit Design and System Verification
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A FPGA-based Demonstrator for Safety-Critical Applications
Christian Fibich, Peter Roessler, Stefan Tauner, Martin Matschnig and Herbert Taucher
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Using Python tools to assist mixed-signal ASIC design and verification methodologies
Evangelos Logaras and Andreas Weitzer
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15:35 - 16:10
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Coffee Break, Exhibition
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| 16:10 - 17:40 |
Session IV: Analog and Mixed-Signal Circuit Design
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Implementation of a Charge-Controlled Method in a Monolithic Integrated CMOS-Chip for Excitation of Retinal Neuron Cells
Andreas Erbslöh, Reinhard Viga, Peter Walter, Rainer Kokozinski and Anton Grabmaier
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Measurement and Comparison of several Pass Transistor Logic Styles in a 350nm technology
Andreas Rauchenecker and Timm Ostermann
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Implementation of an integrated differential Readout Circuit for transistor-based Physically Unclonable Functions
Benjamin Willsch, Kai-Uwe Müller, Qi Zhang, Stefan Dreiner, Alexander Stanitzki, Holger Kappert, Rainer Kokozinski and Holger Vogt
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Survey on Integrated High Power Low Emission Output Stages for Drivers of Low-Frequency Resonant Loads
Herbert Hackl, Mario Auer and Ricardo Erckert
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17:40 - 17:50
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Outlook Austrochip 2018
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