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Austrochip 2016 Conference Program:
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08:00 - 09:00
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Registration and Breakfast
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09:00 - 09:15
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Conference Opening
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| 09:15 - 10:15 |
Keynote Address
- Analog and Digital Signal Processing Electronics for Multi-channel, High Sensitivity Vapor Trace Detection System
Drago Strle
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10:15 - 10:45
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Coffee Break, Exhibition, Poster
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| 10:45 - 12:15 |
Session I: Analog and Power Management
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Advanced Pseudo Differential Amplifier with Output Common Mode Regulation and Phase Shift Retention.
Sagarika Donepudi, Michael Köberle and Wolfgang Horn
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Modeling and Simulation of Digital Control Schemes for Two-Phase Interleaved Buck Converters.
Marc Kanzian, Matteo Agostinelli and Mario Huemer
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High-Efficiency CMOS Buck Converter with Wide Output Voltage Range
Natasa Mitrovic, Reinhard Enne and Horst Zimmermann.
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A 11-bit Integrating Analog to Digital Converter
Darshan Shetty and Pratap Tumkur Renukaswamy.
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12:15 - 14:00
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Lunch, Exhibition, Poster
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| 14:00 - 15:30 |
Session II: RF and Analog
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Analysis and Design of Differential Feedback CG LNA Topologies for Low Voltage Multistandard Wireless Receivers.
Pratap Tumkur Renukaswamy, Vijaya Sankara Rao Pasupureddi and Johannes Sturm
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Threshold Voltage Compensated RF-DC Power Converters in a 40 nm CMOS Technology.
Lukas Zöscher, Peter Herkess, Jasmin Grosinger, Ulrich Muehlmann, Dominik Amschl, Hubert Watzinger and Wolfgang Bösch.
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System-in-Package Matching Network for RF Wireless Transceivers
Graciele Batistell, Timo Holzmann, Hermann Sterner and Johannes Sturm.
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A Capacity-to-Digital Converter Based on a Ring Oscillator with Flicker Noise Reduction
Andres Quintero Alonso, Fernando Cardes Garcia, Luis Hernandez Corporales, Cesare Buffa and Andreas Wiesbauer.
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15:30 - 16:00
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Coffee Break, Exhibition, Poster
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| 16:00 - 17:10 |
Session III: Embedded Systems and Digital
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On Analysis of Software Interrupt Limiters for Embedded Systems by Means of UPPAAL SMC.
Josef Strnadel and Michal Risa
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A Programmable Delay Line for Metastability Characterization in FPGAs.
Thomas Polzer, Florian Huemer and Andreas Steininger.
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An EMI Receiver Model to Minimize Simulation Time of Long Data Transmissions
Herbert Hackl, Bernd Deutschmann.
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17:10 - 17:20
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Outlook Austrochip 2017
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ARGE HFT Program:
-> Download .pdf
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