Austrochip 2009 - Programm

Zeitplan:

• 08:30 - 09:30       Anmeldung und Frühstück
• 09:30 - 09:45       Eröffung
• 09:45 - 10:30       Eingeladener Vortrag
• 10:30 - 11:00       Postersession und Kaffeepause
• 11:00 - 12:20       Vorträge 1-4
• 12:20 - 12:25       Vorstellung IEEE Austria CAS/SSC Chapter
• 12:25 - 12:30       Vorstellung GMS Gesellschaft für Mikroelektronische Systeme im OVE
• 12:30 - 14:00       Mittagessen
• 14:00 - 15:20       Vorträge 5-8
• 15:20 - 16:00       Postersession und Kaffeepause
• 16:00 - 17:20       Vorträge 9-12
• 17:20 - 17:30       Ausblick

Vorträge:

1. Multilevel Signaling Optical Receiver for High-Speed Transmission over Large-Core Step-Index Plastic Optical Fibre
   M. Atef¹, W. Gaberl¹, Member, IEEE, R. Swoboda², H. Zimmermann¹, Senior Member, IEEE
   ¹ Vienna University of Technology, Institute of Electrodynamics, Microwave and Circuit Engineering
   ² A3PICs Electronics Development GmbH
   

2. A 65nm CMOS RF Power Detector with Integrated Offset Storage
   Wolfgang Aichholzer, Johannes Sturm
   Carinthia University of Applied Sciences
   

3. An 11-bit Successive Approximation Analog to Digital Converter Based on a Combined Capacitor-Resistor Network
   Milos Davidovic, Gerald Zach, Horst Zimmermann
   Institute of Electrodynamics, Microwave and Circuit Engineering, Vienna University of Technology
   

4. Design und Entwicklung eines Mixed Signal Prototyping Systems für RFID Applikationen mit Datenraten größer 848 kbit/s
   Markus Auer¹, Edmund Ehrlich¹, Wolfgang Pribyl¹, Albert Missoni², Walter Kargl^{2
   1}Technische Universität Graz
   ² Infineon Technologies AG
   

5. An IP-XACT Library extended with Verification Information for Functionality-based Component Selection
   Christoph Ruggenthaler¹, Christoph Trummer¹, Christian Steger¹, Reinhold Weiß¹, Andreas Schuhai², Markus Pistauer², Damian Dalton^{3
   1}Institute for Technical Informatics, Graz University of Technology, Austria
   ²CISC Semiconductor Design+Consulting GmbH, Austria
   ³School of Computer Science and Informatics, University College Dublin, Ireland
   

6. Investigating Power-Reduction for a Reconfigurable Sensor Interface Johann Glaser, Jan Haase, Markus Damm, Christoph Grimm
   Vienna University of Technology. Institute of Computer Technology
   

7. An Efficient FPGA Implementation of an Arbitrary Sampling Rate Converter for VoIP
   Peter Brunmayr¹, Hans-Dieter Wohlmuth², Jan Haase^{1
   1}Institute of Computer Technology, Vienna University of Technology
   ²Frequentis AG, A-1100 Vienna, Austria
   

8. Weltweit kleinste, voll integrierte Lösung zur Uhrensynchronisation nach IEEE 1588 auf Schicht 2
   R. Höller¹, H. Muhr², N. Kerö², A. Gröblinger¹, Ch. Kutschera¹, Ch. Veigl¹, Ch. Weiß¹, P. Rössler^{1
   1}Fachhochschule Technikum Wien
   ²Oregano Systems GmbH
   

9. A Behavioral Modeling Approach for Jitter Analysis in Charge-Pump PLLs
   Stefan Erb, Wolfgang Pribyl
   Institute of Electronics, Graz University of Technology
   

10. Comparative study of linear and non-linear integrated control schemes applied to a Buck converter for mobile applications
    R. Priewasser¹, M. Agostinelli¹, S. Marsili², D. Straeussnigg², M. Huemer^{1
    1}Klagenfurt University
    ²Infineon Technologies Austria AG
    

11. Evaluating the Impact of using Fixed-Point Arithmetic on the Precision and Implementation of the Fit-to-Sine Algorithm on an FPGA
    Andreas Weiss
    EADS Defence and Security
    

12. Immunity Scan - Neuartige Untersuchungsmethode zum Lokalisieren von störempfindlichen Schaltungsblöcken in ICs
    Dieter Maier, Bernhard Weiss, Rainer Minixhofer
    Austriamicrosystems AG
    

Poster:

• Compact Hardware Implementations of the SHA-3 Candidates ARIRANG, BLAKE, Grøstl, and Skein
  Stefan Tillich, Martin Feldhofer, Wolfgang Issovits, Thomas Kern, Hermann Kureck, Michael Mühlberghuber, Georg Neubauer, Andreas Reiter, Armin Köfler, and Mathias Mayrhofer
  Graz University of Technology
  Institute for Applied Information Processing and Communications
  

• Low-Power High-Speed Decimation Filter in 65 nm CMOS
  Oleksandr Melnychenko, Sergii Zaiets, Manfred Ley
  Fachhochschule Kärnten, School of Systems Engineering
  

• Design Of A Fully Reconfigurable Bandpass Filter For Use In Cochlear Implants
  Paul Faragó¹, Peter Söser², Sorin Hintea^{1
  1}Technical University of Cluj-Napoca, Romania
  ²Graz University of Technology, Austria

• Stromquelle mit temperaturkompensiertem Referenzwiderstand
  Stephan Dobretsberger
  austriamicrosystems AG
  

• A Flexible On-Chip Test Structure with Single Pin Serial Interface
  Matthias Steiner
  austriamicrosystems AG
  

• Coupling Asynchronous Signals into Asynchronous Logic
  Markus Ferringer
  Institute of Computer Engineering, Embedded Computing Systems Group, Vienna University of Technology
  

• Auswirkungen kapazitiver Kopplungen in Delta-Sigma-Modulatoren mit Switched-Capacitor-Feedback
  Christoph B. Wurzinger
  Technische Universität Graz, Institut für Elektronik
  

• Hardware Acceleration of RNA Folding
  Manuela Midl, Christian Netzberger
  FH-Joanneum Kapfenberg
  

• Using SRAMs as Physical Unclonable Functions
  Christoph Böhm, Maximilian Hofer
  Institute of Electronics, Graz University of Technology
  

• A SystemC Design Pattern for the Cosimulation of Transaction-Level and Refined Cycle-Callable Models
  Rainer Findenig¹, Wolfgang Ecker^{2
  1} FH Hagenberg, Hagenberg, Austria
  ² Infineon Technologies AG, Munich, Germany
  

• A Low-Voltage Charge Sampling Mixer for Direct Conversion at 1GHz in 65nm CMOS Technology
  Kurt Schweiger, Horst Zimmermann
  Institute of Electrodynamics, Microwave and Circuit Engineering
  Vienna University of Technology